summaryrefslogtreecommitdiff
path: root/DRAM.cpp
blob: 5a0faac398dcc6ea8c90be12a41040937763c3bd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
#include "DRAM.h"


DRAM::DRAM() {
    buf = new uint8_t[16*1024];
}
DRAM::~DRAM() {
    delete[] buf;
}
void DRAM::apply(
    CData clk,
    CData we,
    uint64_t claddr,
    VlWide<4>* cldata) {
    this->prev_clk = this->clk;
    this->clk = clk;
    this->we = we;
    this->claddr = claddr;
    this->cldata = cldata;
}

void DRAM::eval() {
    if (!prev_clk && clk)
        posedge_clk();
}

void DRAM::posedge_clk() {
    // Align address on cache line address boundary
    claddr &= ~0xF;

    // Get a word based pointer to the memory
    uint32_t *base = (uint32_t*)(buf + claddr);

    if (we) {
        printf("DRAM: write at %llx: %x%x%x%x\n",
            claddr,
            cldata->at(3),
            cldata->at(2),
            cldata->at(1),
            cldata->at(0)
        );

        // Write the memory from the bus
        for (int i = 0; i < 4; i++)
            base[i] = cldata->at(i);
    } else {
        // Write the bus from the memory
        for (int i = 0; i < 4; i++)
            cldata->at(i) = base[i];

        printf("DRAM: read at %llx: %x%x%x%x\n",
            claddr,
            cldata->at(3),
            cldata->at(2),
            cldata->at(1),
            cldata->at(0)
        );
    }
}