`include "arbiter.v"
module system(
    input clk,

    // DRAM device
    output[63:0] mem_claddr,
    output mem_we,
    inout[127:0] mem_cldata);

    reg [3:0] request = 'b0001;

    arbiter arbiter(
        .clk(clk),
        .request(request),
        .grant()
    );

    reg[127:0] counter = 0;
    assign mem_we = 0;
    assign mem_claddr = 17;
    assign mem_cldata = 42;

    always @(posedge clk) begin
        if (counter > 1100)
            request <= 0;
        else if (counter > 1050)
            request <= 'b0011;
        else if (counter > 1000)
            request <= 'b0100;
        
        counter <= counter + 1;
    end
endmodule